MODE=WS0, BUSSTRATEGY=CPU
Read Control Register
| MODE | Read Mode 0 (WS0): Zero wait-states inserted in fetch or read transfers. 1 (WS1): One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz. 2 (WS0SCBTP): Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex’ conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty. 3 (WS1SCBTP): One wait-state access with SCBTP enabled. 4 (WS2): Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz. 5 (WS2SCBTP): Two wait-state access with SCBTP enabled. |
| IFCDIS | Internal Flash Cache Disable |
| AIDIS | Automatic Invalidate Disable |
| ICCDIS | Interrupt Context Cache Disable |
| EBICDIS | External Bus Interface Cache Disable |
| RAMCEN | RAM Cache Enable |
| BUSSTRATEGY | Strategy for bus matrix 0 (CPU): undefined 1 (DMA): undefined 2 (DMAEM1): undefined 3 (NONE): undefined |